The folded-cascode amplifier is a widely used topology in analog circuits. Its advantage over other amplifier types is in increased input common-mode range that normally includes one of the supply rails. A class AB type amplifier is characterized in that each half conducts through more than a half cycle but less than a full cycle, and normally is implemented by a push-pull output transistor pair.
Shown in FIG. 1 is a circuit diagram of a class AB folded-cascode amplifier circuit 10 of a type known in the prior art, which comprises an input differential pair circuit 12, a cascode circuit 14 that includes cascode transistors M13, M14 and a load circuit comprising current mirror 16, and a class AB output stage 18 powered from supply lines V+, V−. Input circuit 12 is a differential transistor amplifier in the form of a differential input transistor pair M11, M12 having their gates receiving the input signal at VINP and VINM to be amplified, their drains connected to current sources I2, I3 and their sources connected commonly to a source of tail current I1. Cascode transistors M13, M14 are connected to the input transistor pair M11, M12 and current sources 12, 13, and function as current buffers. A gate voltage VB1 produced by a source of bias voltage (not shown) is used to bias cascode transistors M13, M14 such that differential input transistor pair M11, M12 remain in saturation over their common-mode range while at the same time the headroom requirement for current sources I2, I3 are satisfied and cascode transistors M13, M14 are biased into saturation.
Coupled to cascode transistors M13, M14 and comprising the load 16 of the input differential pair circuit 12, is a wide swing cascode current mirror 16 that consists of transistors M15-M18, configured as shown with an interconnection between the gate of M15 and drain of M17. The current mirror 16 alternatively could be configured as other than as a wide-swing cascode type shown by interconnecting the gate and drain only of M15.
Class AB output stage 18 comprises complementary driver transistors M2P, M2N, serially connected as shown, with common node at VOUT driving load RL, CL. The driver transistors M2P, M2N are controlled by a conventional class AB control circuit 19. A Miller compensation network comprising capacitors CC1, CC2 and RN1, RN2 between the drains and gates of M2P, M2N, is implemented in conventional form in the class AB topology described.
In the simple Miller compensation arrangement, the amplifier is stabilized through RC compensation networks which split the first and second poles of the uncompensated amplifier further apart. In more detail, the added capacitors CC1, and CC2 make the first pole occur at a lower frequency and the second pole occur at a higher frequency. The simple Miller compensation also creates a zero whose location can be tuned by nulling resistors RN1, and RN2.
However, a problem that arises with simple Miller compensation is in the feedforward path from node A and node B to the output node. Because in this configuration the noninverting signal can pass to the output node, degradation in the frequency response of the amplifier occurs. Specifically, Miller compensation capacitors CC1, and CC2 become feedforward paths for high-frequency signals and can lead to unstable operation. In addition, the size of the capacitors can be large, consuming large die area.
Although provision of nulling resistors RN1, and RN2 in the feedforward paths reduces the magnitude of the feedforward signal, the problem is only mitigated to a limited extent. As the size of the nulling resistors is increased, the introduced LHP zero moves closer to the crossover frequency, degrading gain margin.
Cascode compensation to improve the gain-bandwidth product of amplifiers by blocking the feedforward signal with a current buffer in the compensation path has been practiced, using an explicit (added) current buffer (see Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE Journal of Solid State Circuits, Vol. SC-18, No 6, December 1983, pp 629-622) or embedded (existing) cascode transistor in the input stage 12 for Class A amplifiers (see Ribner and Copeland, IEEE Journal of Solid State Circuits, Vol. SC-19, No 6, December 1984, pp 919-925). Compensation of fully differential operational amplifiers is also presented and analyzed by Hurst et al., IEEE Transactions on Circuits and Systems—1: Regulator Papers, Vol. 51, No. 2, February 2004, pp. 275-285 and Yao et al., Fast-settling CMOS Two-stage Operational Transconductance Amplifiers and Their Systematic Design, IEEE International Symposium on Circuits and Systems, Vol. 2, pp. II-839—II-842, all incorporated herein by reference. These approaches, however, are not applicable to class AB amplifiers. It would be desirable to provide a class AB folded-cascode amplifier topology having improved gain-bandwidth performance.